1. Field of the Invention
The present invention relates to the field of high speed digital circuits, in particular, high speed digital circuits based on CMOS technology. More specifically, the present invention relates to a method and apparatus for digitally compensating digital clock skew for high speed digital circuits in a digital system, such as a data instrumentation system.
2. Background
In a digital system having a number of digital circuits, such as a data instrumentation system, as the digital clock passes through one of the digital circuits, the clock high time tends to either shrink or expand, resulting in the skewing of the digital clock. In some CMOS circuits, the skewing of the digital clock, i.e. variations in the clock high time and clock low time, can be more than two (2) or three (3) nanoseconds (ns) depending on the loading of the particular CMOS circuits. A 2-3 ns skew can be significant, depending on the length of the digital clock period. Experience has shown that 2-3 ns skew actually become limiting to either the speed of the system or the complexity of the logic as the digital clock period approaches the range of 10-15 ns. The digital clock period approaches the range of 10-15 ns, as the operating speed approaches about 66 MHZ. As a result, 66 MHZ has become the de facto maximum operating speed for many digital designs based on CMOS high speed circuits under the current 0.8 micron technology. Since it is obviously beneficial to be able to improve and push the maximum operating speed of digital designs based on CMOS high speed circuits beyond 66 MHZ, it is desirable to be able to digitally compensate the digital clock skew as it travels through one CMOS high speed circuit onto another.
Additionally, for a digital system such as a data instrumentation system, it is often operated at different speeds at different times. However, depending on the design and the load, the CMOS high speed circuits in the digital system require a certain minimum amount of high and low time in each clock period in order to function properly regardless of the operating frequency. Thus, it is further desirable to be able to ensure that the minimum amount of high and low time are provided when digitally compensating digital clock skew.
As will be disclosed, the present invention provides such a method and apparatus which advantageously achieves the desirable results described above. As will be obvious from the descriptions to follow, the present invention has particular application to high speed data instrumentation systems.